[Eecs-jobs] Intel Looking for an Undergrad Intern

Sun Apr 20 14:34:34 PDT 2008

-----Original Message-----
From: musah at eecs.oregonstate.edu [mailto:musah at eecs.oregonstate.edu] 
Sent: Friday, April 18, 2008 6:48 PM
To: tinab at eecs.oregonstate.edu
Cc: wesley.h.kwong at intel.com; moon, un-ku
Subject: Fwd: Looking for an undergrad intern

Hello Ms Battern,

I am one of Professor Moon's students. Wesley is a friend at Intel and  
I work with him on my internships with the Communications Circuits Lab  
(CCL) at Intel. They are looking for an undergraduate summer intern,  
and will be glad if you could send out the job posting below to  
undergraduates in EECS.

Wesley will like interested applicants to send their resumes to him  
directly via "Kwong, Wesley H" <wesley.h.kwong at intel.com>

Thank you.

Tawfiq Musah

----- Forwarded message from wesley.h.kwong at intel.com -----
     Date: Fri, 18 Apr 2008 16:59:13 -0700
     From: "Kwong, Wesley H" <wesley.h.kwong at intel.com>
Reply-To: "Kwong, Wesley H" <wesley.h.kwong at intel.com>
  Subject: Looking for an undergrad intern
       To: musaht at onid.orst.edu

<<snip>>

CAD Engineer Intern - 551538

Business Group
The mission of the Corporate Technology group is to drive Intel's
technology leadership. This includes coordinating research and
development among several business groups and aligning Intel's
strategies and technologies with industry needs. The goal is to
accelerate the convergence of computing and communications.

Responsibilities and Details

Description

In this position, you will be responsible for evaluating, creating,
testing, and documenting CAD flows to improve productivity for CCL
custom circuit designers. The CAD flows specifically will be for
enabling a selected set of commercial industry standard tools work on
Intel's proprietary batch scheduling system in a robust and useable
manner that are compatible with CCL's existing CAD flows. You may also
be requested to debug problems with the existing CAD flows occasionally.

Qualifications
You should be progressing towards a Bachelor of Science degree in
Electrical Engineering, Computer Engineering, or Computer Science.
Additional qualifications include:
- Problem solving, high quality software coding, debug, documentation
skills, and excellent communication skills
- Good knowledge of the UNIX operating system
- Intimacy with shell scripting (C and Bourne shell), Perl programming
- Ability to pick up additional scripting languages as required
(specifically the Cadence DFII SKILL language)
- Some basic understanding of batch scheduling systems
- Basic analog circuit design
- Integrated circuit design experience (VLSI circuit design class,
long-channel modelling class, monolithic amplifier design class) and
HSPICE knowledge would be an added advantage

Regards,

Wesley H Kwong
CAD Engineer
CTG/CTL/CCL
Intel Corporation
MS: JF3-220
2111 NE 25th Avenue
Hillsboro, OR 97124

Phone: +1 (503) 712-4564
email: wesley DOT h DOT kwong AT intel DOT com

----- End forwarded message -----